Printed wiring boards having a highly dense mounted structure are known to have structures in which printed substrates are fashioned in multiple layers and semiconductor IC chips are embedded therein (see Japanese Patent Application Laid Open No. 2001-237347). Methods used for exposing a pad electrode of a semiconductor IC chip embedded into a printed wiring substrate include a method whereby a laser is used to form a via hole directly above the pad electrode (see Japanese Patent Application Laid Open No. 9-321408); and a method in which the entire surface of a resin layer in which the semiconductor IC chip is encapsulated is polished and the pad electrode is exposed (see Japanese Patent Application Laid Open No. 2001-250902).
The following problems are encountered in the method for exposing an electrode pad by using a laser to form a via hole (Japanese Patent Application Laid Open No. 9-321408). First, when a via hole is formed directly above a pad electrode of a semiconductor IC chip, the semiconductor IC chip will be damaged if the via hole is formed by laser processing in the same manner as a via hole in a regular IC substrate because the semiconductor IC chip will be directly subjected to thermal shock, and the yield will deteriorate. Particularly, since the pad electrodes of the semiconductor IC chip are disposed at a fine pitch, the precision with which the processing is performed is necessarily very high, and certain laser devices may not be capable of such precision. Since the number of via holes increases along with the number of pad electrodes on a semiconductor IC chip, the production capacity of the laser device inevitably fluctuates, and productivity declines.
The following problems are encountered in the method for exposing a pad electrode of a semiconductor IC chip by polishing the entire surface of an encapsulating resin layer (Japanese Patent Application Publication No. 2001-250902). When the entire surface of the encapsulating resin is polished, the semiconductor IC chip is often damaged due to the load applied to the substrate, and a reduced yield results. The range within which the degree of polishing can be set is limited, and it is extremely difficult to minimize polishing variation. When a semiconductor IC chip having pad electrodes of varying height is encapsulated, not all of the pad electrodes can be exposed. When a semi-additive method is used to form electrical connections between the pad electrodes and a wiring pattern, electroless plating and electroplating must be sequentially performed on the polished resin surface. However, reliability declines due to the low adhesive strength between the polished resin surface and the electroless plating.
Furthermore, semiconductor IC chips embedded in substrates are different from other electronic components, and comprise many expensive parts. Therefore, a demand has arisen for a manufacturing method that does not damage the semiconductor IC chips and offers stable yields.